Emulation systems typically were formed using emulation integrated circuits, including programmable logic devices (PLDs), such as general-purpose field programmable gate arrays (FPGAs), without integrating debugging facilities. To emulate a design on such an emulation system, the design would be “realized” by compiling a formal description of the design, partitioning the design into subsets, mapping various subsets to the logic elements (LEs) of the emulation integrated circuits of various logic boards of the emulations system, and then configuring various interconnects to interconnect the logic elements. The partitioning and mapping operations typically would be performed on workstations that were part of or complementary to the emulation systems, while the configuration information correspondingly would be downloaded onto the logic boards hosting the emulation integrated circuits, and then onto the emulation integrated circuits.
During emulation of a design in a PLD, such as a field programmable device (FPD), test stimuli are generated on the workstation or on a service board of the emulation system under control of the workstation, and then transferred to various logic boards for input into the PLDs for application to the various netlists of the design being emulated. Correspondingly, state data of various circuit elements, which may include data of interest of the design being emulated, would be read out of the applicable PLDs and then transferred off the logic boards for analysis on the workstation.
With advances in integrated circuit and emulation technology, other emulation systems began to employ PLDs specifically designed for emulation purposes. These special PLDs typically would include a substantial amount of on-chip reconfigurable logic elements, reconfigurable interconnects, memory, and debugging resources. As advances in the technology field continue, an increasing number of these on-chip reconfigurable logic elements, interconnects, memory, and debugging resources are packed into each PLD. As the number of reconfigurable emulation resources being included into a PLD increase, so does the number of control signals that have to configure each PLD.
Accordingly, there is an increasing amount of configuration data to be loaded for reconfigurable interconnect resources of each PLD. Emulation of a circuit design may require interconnecting many LEs within the same PLD as well as interconnecting those LEs with many other LEs residing on different PLDs or LEs residing on separate logic boards, each interconnection requiring configuration of reconfigurable interconnect resources to make the appropriate interconnection. Thus, there becomes a problem of how to load and/or compress all of this configuration data. More configuration memory is required to be downloaded to configure the increased number of reconfigurable interconnect resources. Thus, an improved approach to loading configuration data and compression of that data is desired.